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63 mhz dual programmable filters and variable gain amplifiers preliminary technical data adrf6518 rev. pra document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assum ed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or pat ent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc . all rights reserved. technical support www.analog.com features matched pair of programmable filters and triple vgas continuous gain control range: 72 db digital gain control: 30 db 6- pole butterworth filter: 1 mhz to 63 mhz in 1 mhz steps, 1 db corner frequency preamplifier and post amplifier gain steps peak detector filter by pass mode, ? 3 db bandwidth ( bw ) vga 2 and vga 3 21 db /12 db gain: 350 mhz /700 mhz imd3: >65 dbc for 1.5 v p - p composite output hd2, hd3: >65 dbc for 1.5 v p - p out put differential input and output flexible output and input common - mode ranges optional dc output offset correction spi programmable filter corners and gain steps single 3.3 v supply operation w ith power - down feature applications baseband i/q receivers diversity receivers adc drivers point - to - point and point - to - multipoint radio s instrumentation medical functional block dia gram figure 1 . general description the adrf6518 is a matched pair of fully differential low noise and low distortion programmable filters and variable gain ampli fiers (vgas). each channel is capable of rejecting large out - of - band interferers while reliably boosting the wanted signal, thus reducing the bandwidth and resolution requirements on the analog - to - digital converters (adcs). the excellent matching between c hannels and their high spurious - free dynamic range over all gain and bandwidth settings make the adrf6518 ideal for quadrature - based (iq) communication systems with dense constellations, multi ple carriers, and nearby interferers. the various amplifier gains, filter corners and other features are all programmable via a serial port interface ( spi ) port. the first vga that precedes the filters offers 24 db of continuous gain control with fixed gain options of 9 db, 12 db, and 15 db , and sets a differential input impedance of 400 . the filters provide a six - pole butterworth response with 1 db corner frequencies from 1 mhz to 63 mhz in 1 mhz steps. for operation beyond 63 mhz, the filter can be disa bled and complete ly bypassed via the spi. a wide band peak detector is available to monitor the peak signal at the filter inputs. the pair of vgas that follow the filters each provide s 24 db of continuous gain control with fixed gain options of 12 db, 15 db , 18 db, and 21 db. the output buffers offer a n additional option of 3 db or 9 db gain and provide a differential output impedance of less than 10 ?. they are capable of driving 3 v p - p into 1 k? loads at better than 65 dbc hd3. the output common - mode volt age defaults to vps/2 and can be adjusted down to 900 mv by driving the high impedance vocm pin. independent, built - in dc offset correction loops for each channel can be disabled via the spi if fully dc - coupled operation is desired. the high - pass corner fr equency is deter - mined by external capacitors on the ofs1 and ofs2 pins and the postfilter vga gain. the adrf6518 operates from a 3.15 v to 3.45 v supply and consumes a maximum supply current of 400 ma. when fully disabled, it consumes <10 ma. the adrf6518 is fabricated in an advanced silicon - germanium bicmos process a nd is available in a 32 - lead, exposed pad lfcsp. performance is specified over the ?40c to +85c temperature range.
adrf6518 preliminary technical data rev. pra | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 specifications ..................................................................................... 3 timing diagrams .......................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 filter mode .................................................................................... 8 bypass mode ............................................................................... 16 mixed power and filter modes ................................................. 19 register map and codes ................................................................ 20 theory of operation ...................................................................... 21 input vgas ................................................................................. 21 peak detector .............................................................................. 21 programmable filters ................................................................. 22 variable gain amplifiers (vgas) ............................................ 22 output buffers/adc drivers ................................................... 23 dc offset compensation loop ................................................ 23 programming the adrf6518 ................................................... 23 noise characteristics ................................................................. 23 distortion characteristics ......................................................... 24 maximizing the dynamic range ............................................. 24 key parameters for quadra ture - based receivers .................. 25 applications information .............................................................. 26 basic connections ...................................................................... 26 supply decoupling ..................................................................... 26 input signal path ........................................................................ 26 output signal path ..................................................................... 26 dc offset compensation loop enabled ................................ 26 common - mode bypassing ....................................................... 27 serial port connections ............................................................. 27 e nable/disable function ........................................................... 27 gain pin decoupling ................................................................. 27 peak detector connections ...................................................... 27 error vector magnitude (evm) performance ........................... 27 evm test setu p .......................................................................... 27 evaluation board ............................................................................ 28 evaluation board control software ......................................... 28 schematics and artwork ........................................................... 29 outline dimensions ....................................................................... 34 orderin g guide .......................................................................... 34
preliminary technical data adrf6518 rev. pra | page 3 of 36 specifications vps = 3.3 v, t a = 25c, z load = 1 k?, unless otherwise noted, vga1 m ax imum g ain c ode = 00, vga2 maximum g ain c ode = 00, vg3 maximum g ain c ode = 00, posta mp g ain c ode = 1, o ffset c ompensation loop enabled, l ow/ h igh p ower mode . table 1. parameter test conditions/comments min typ max unit frequency response, filter bypass mode ?3 db bandwidth vga2 and vga3 21 db digital gain setting 350 mhz vga2 and vga3 12 db digital gain setting 700 mhz frequency response low - pass corner frequency, f c 6- pole butterworth filter, 0.5 db bandwidth 1 63 mhz step size 1 mhz corner frequency absolute accuracy over operating temperature range 8 % f c corner frequency matching channel a and channel b at same gain and bandwidth settings 0.5 % f c pass - band ripple 0.5 db p -p gain matching channel a and channel b at same gain and bandwidth settings 0.1 db group delay variation from mid band to peak corner frequency = 1 mhz 135 ns corner frequency = 30 mhz 11 ns group delay matching channel a and channel b at same gain corner frequency = 1 mhz 5 ns corner frequency = 30 mhz 0.2 ns stop - band rejection relative to pass band 2 f c 30 db 5 f c 75 db input stage inp1, inm1, inp2, inm2, vicm maximum input swing at minimum gain, vgn1 = 0 v 4.0 v p -p differential input impedance 400 input common - mode range 1.5 v p - p input voltage, hd3 > 65 dbc (vpi = 3.3 v) 1.35 1.95 v input pins left floating 1.5 v peak detector vpk, ravg output scaling relative to peak voltage at filter input 1 v/v pk gain control vgn1, vgn2, vgn3 gain range max imum d igital g ains ?6 + 66 db min imum d igital g ains ? 36 + 36 db voltage attenuation range each attenuator; v gain from 0 v to 1 v ?24 0 db gain slope 30 mv/db gain error v gain from 300 mv to 800 mv 0.2 db output stage opp1, opm1, opp2, opm2, vocm maximum output swing at maximum gain, r load = 1 k 3 v p -p hd2 > 65 dbc, hd3 > 65 dbc 1.5 v p -p differential output impedance < 10 output dc offset inputs shorted, offset loop enabled <20 mv output common - mode range 1.5 v p - p output voltage 0.9 vps ? 1.2 v vocm left floating vps/2 v vocm input impedance 23 k
adrf6518 preliminary technical data rev. pra | page 4 of 36 parameter test conditions/comments min typ max unit noise/distortion corner frequency = 31 mhz output noise density max imum g ain at f c /2 ? 105.5 dbv/hz min imum g ain at f c /2 ? 105.5 dbv/hz second harmonic, hd2 10 mhz fundamental, 1.5 v p - p at vga1 output voltage vga2, vga3 at min imum gain (digital and analog) 66 dbc third harmonic, hd3 10 mhz fundamental, 1.5 v p - p at vga1 output voltage vga2, vga3 at min imum gain (digital and analog) 66 dbc imd3 f1 = 500 khz, f2 = 550 khz, 1.5 v p - p composite output voltage 65 dbc corner frequency = 63 mhz output noise density minimum gain ?105.5 dbv/hz maximum gain ?105.5 dbv/hz second harmonic, hd2 20 mhz fundamental, 1.5 v p - p at vga1 output voltage vga2, vga3 at minimum gain (digital and analog) 56 dbc third harmonic, hd3 20 mhz fundamental, 1.5 v p - p at vga1 output voltage vga2, vga3 at minimum gain (digital and analog) 66 dbc digital logic le, clk, data, sdo input high voltage, v inh >2 v input low voltage, v inl <0.8 v input current, i inh /i inl <1 a input capacitance, c in 2 pf spi timing le, clk, data, sdo f sclk 1/t sclk 20 mhz t dh data hold time 5 ns t ds data setup time 5 ns t lh le hold time 5 ns t ls le setup time 5 ns t pw clk high pulse width 5 ns t d clk to sdo delay 5 ns power and enable vps, vpsd, com, comd, enbl supply voltage range 3.15 3.3 3.45 v total supply current enbl = 5 v maximum bw setting, high power filter 400 ma minimum bw setting, low power filter 360 ma filter bypassed, high power mode 260 ma filter bypassed, low power mode 230 ma disable current enbl = 0 v 9 ma disable threshold 1.6 v enable response time delay following enbl low -to - high transition 20 s disable response time delay following enbl high -to - low transition 300 ns
preliminary technical data adrf6518 rev. pra | page 5 of 36 timing diagrams figure 2. write mode timing diagram figure 3. read mode timing diagram write bit msb - 2 b2 lsb t ds t dh t lh t ls t pw t clk notes 1. the first data bit determines whether the part is writing to or reading from the internal 8-bit register. for a write operation, the first bit should be a logic 1. the 8-bit word is then written to the data pin on consecutive rising edges of the clock. clk le dat a b3 b7 msb b4 b5 b6 0 9422-003 don?t care don?t care read bit don?t care don?t care don?t care don?t care don't care b2 lsb clk le data sdo notes 1. the first data bit determines whether the part is writing to or reading from the internal 8-bit register. for a read operation, the first bit should be a logic 0. the 8-bit word is then registered at the sdo pin on consecutive falling edge s of the clock. b3 b4 b5 b6 b7 msb don?t care don?t care t ds t dh t lh t ls t pw t clk t d 09422-004
adrf6518 preliminary technical data rev. pra | page 6 of 36 absolute maximum rat ings table 2. parameter rating supply voltages, vps, vpsd 3.45 v enbl, le, clk, data, sdo vpsd + 0.5 v inp1, inm1, inp2, inm2, vicm vps + 0.5 v opp1, opm1, opp2, opm2, vocm vps + 0.5 v ofs1, ofs2, vpk, ravg vps + 0.5 v vgn1, vgn2, vgn3 vps + 0.5 v internal power dissipation 1.25 w ja (exposed pad soldered to board) 37.4c/w maximum junction temperature 150c operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
preliminary technical data adrf6518 rev. pra | page 7 of 36 pin configuration and function descriptions figure 4 . pin configuration table 3 . pin function descriptions pin o. mnemonic description 1 vpsd digital positive supply voltage: 3.15 v to 3.45 v. 2 comd digital common. connect to external circuit common using the lowest possible impedance. 3 le latch enable. spi programming pin. ttl levels: v low < 0.8 v, v high > 2 v. 4 clk spi port clock. ttl levels: v low < 0.8 v, v high > 2 v. 5 data spi data input. ttl levels: v low < 0.8 v, v high > 2 v. 6 sdo /rst spi data output (sdo). ttl levels: v low < 0.8 v, v high > 2 v. peak detector reset (rst). a >25 ns high pulse is require d on this pin to reset the detector. 7 vicm /ac input common - mode reference (vicm). vpi/2 reference output for optimal common - mode level to drive the differential inputs. ac coupling/internal bias activation (ac). pull this pin low for ac coupling of the inputs. 8 vpi input stage supply voltage: 3.15 v to 5.25 v. connect to vps if input common - mode range is narrow (1.35 v to 1.95 v). connect to 5 v if input common - mode up to 3.1 v is desired. 12, 16, 25, 29 vps analog positive supply voltage: 3.15 v to 3.45 v. 9, 19, 22 com analog common. connect to external circuit common using the lowest possible impedance. 10, 11, 30, 31 inp 2 , inm 2, inm1, inp1 differential inputs. 400 input impedance. 13 vpk peak detector output . scaling of 1 v/v pk differential at filter inputs. the b igger peak of two channels is reported. 14 vgn2 vga2 analog gain control. 0 v to 1 v, 30 mv/db gain scaling. 15, 26 ofs2, ofs1 offset correction loop compensation capacitors. connect capacitors to circuit common. 17, 18, 23, 24 opp 2 , opm 2, opm1, opp1 differential outputs. <10 output impedance. common - mode range is 0.9 v to vps ? 1.2 v; default is vps/2. 20 vocm output common - mode setpoint. defaults to vps/2 if left open. 21 vgn3 vga3 analog gain control. 0 v to 1 v, 30 mv/db gain scaling. 27 vgn1 vga1 analog gain control. 0 v to 1 v, 30 mv/d b gain scaling. 28 ravg peak detector time - constant resistor . connect this pin to vps. leave open for longest hold time. ravg range is to 1 k . 32 enbl chip enable. pull high to enable. ep exposed pad. connect the exposed pad to a low impedance ground pad.
adrf6518 preliminary technical data rev. pra | page 8 of 36 typical performance characteristics filter mode vps = 3.3 v, t a = 25c, z load = 400 , low power mode, digital gain code b[8:2] = 1111110, and b1 = 0, unless otherwise noted. figure 5. in-band gain vs. vgn1 over supply and temperature (bw setting = 63 mhz) figure 6. in-band gain vs. vgn2 over supply and temperature (bw setting = 63 mhz) figure 7. in-band gain vs. vgn3 over supply and temperature (bw setting = 63 mhz) figure 8. gain conformance vs. vgn1 over supply and temperature (bandwidth setting = 63 mhz) figure 9. gain conformance vs. vgn2 over supply and temperature (bandwidth setting = 63 mhz) figure 10. gain conformance vs. vgn3 over supply and temperature (bandwidth setting = 63 mhz)
preliminary technical data adrf6518 rev. pra | page 9 of 36 figure 11. gain vs. freque ncy over vgn1/vgn2/vgn3 (bw setting = 63 mhz) figure 12. digital gain vs. frequency; vgn1/vgn2/vgn3 = 0 v (bw setting = 63 mhz) figure 13. gain matching betwee n channels vs. vgn1/vgn2/vgn3 (bw setting = 63 mhz) figure 14. op1db vs. gain (bandwidth setting = 63 mhz) figure 15. frequency response over supply and temperature; vgn1/vgn2/vgn3 = 0 v figure 16. frequency response vs. bw setting (linear); vgn1/vgn2/vgn3 = 0 v
adrf6518 preliminary technical data rev. pra | page 10 of 36 figure 17. frequency response vs. bandwidth setting (log); vgn1/vgn2/vgn3 = 0 v figure 18. group delay vs. frequency; vgn1/vgn2/vgn3 = 0 v figure 19. iq group delay mismatch vs. frequency (bw = 7 mhz and 15 mhz) figure 20. iq group delay mismatch vs. frequency (bw = 30 mhz and 60 mhz) figure 21. iq amplitude mismatch vs. frequency; vgn1/vgn2/vgn3 = 0 v figure 22. noise figure vs. analog gain over digital gain; bw = 63 mhz
preliminary technical data adrf6518 rev. pra | page 11 of 36 figure 23. noise figure vs. an alog gain over bw setting; digital gain = 0000001 figure 24. output noise density vs. analog gain over digital gain; bw = 63 mhz figure 25. output noise density vs . gain over bandwidth setting; digital gain = 0000001 figure 26. output noise densit y vs. frequency; bw = 7 mhz, digital gain = 0000001 figure 27. output noise density vs. frequency; bw = 60 mhz, digital gain = 0000001 figure 28. output noise density vs. input cw block level; bw = 63 mhz, digital gain = 0000001
adrf6518 preliminary technical data rev. pra | page 12 of 36 figure 29. hd2 and hd3 vs. gain over supply and temperature; bw = 63 mhz, 16 mhz fundamental tone, digital gain = 1111110 figure 30. hd2 and hd3 vs. gain over supply and temperature; bw = 63 mhz, 16 mhz fundamental tone, digital gain = 1111111 figure 31. hd2 and hd3 vs. gain over vocm; bw = 63 mhz, 16 mhz fundamental tone figure 32. hd2 and hd3 vs. vpk, dc-coupled; bw = 63 mhz, 16 mhz fundamental tone figure 33. hd2 and hd3 vs. vpk, ac-coupled; bw = 63 mhz, 16 mhz fundamental tone figure 34. input ip2 and ip3 vs.vga1 gain (ac-coupled)
preliminary technical data adrf6518 rev. pra | page 13 of 36 figure 35. in-band oip3 vs. v out (v p-p) over temperature; bw = 63 mhz, 30 mhz and 31 mhz tones, digital gain = 0000001 figure 36. in-band imd3 vs. composite output voltage over gain; 30 mhz and 31 mhz tones , digital gain = 1111110 figure 37. in-band imd3 vs. composite output voltage over gain; 30 mhz and 31 mhz tones , digital gain = 0000001 figure 38. out-of-band input ip2, imd2 vs. pin over digital gain; 115 mhz and 130 mhz tones figure 39. out-of-band input ip3, imd3 vs. pin over digital gain; 115 mhz and 130 mhz tones figure 40. current consumption ov er bandwidth over digital gain
adrf6518 preliminary technical data rev. pra | page 14 of 36 figure 41. current consumption vs. temperature over digital gain figure 42. common mode reje ction ratio vs. frequency figure 43. detector time domain response figure 44. gain step response figure 45. detector output vs. pin over temperature; vgn1 = 0.5 v, vgn2 = vgn3 = 0 v figure 46. detector hold time vs. ravg
preliminary technical data adrf6518 rev. pra | page 15 of 36 figure 47. detector reset time domain response
adrf6518 preliminary technical data rev. pra | page 16 of 36 bypass mode vps = 3.3 v, t a = 25c, z load = 400 , high power mode, digital gain code b8:b2 = 1111110, and b1 = 0 unless otherwise noted. figure 48. frequency response over supply and temperature figure 49. group delay vs. frequency figure 50. output noise density vs . frequency over analog gains; digital gain = 0000001 figure 51. channel isolation (outa to outb) vs. frequency figure 52. noise figure vs. analog gain over digital gain figure 53. output noise density vs. analog gain over digital gain
preliminary technical data adrf6518 rev. pra | page 17 of 36 figure 54. hd2 vs. gain over supply and temperature figure 55. hd3 vs. gain over output common-mode voltage figure 56. hd3 vs. gain over supply and temperature figure 57. hd2 vs. gain over output common-mode voltage figure 58. hd2/3 vs. composite output voltage over vocm; vgn1/vgn2/vgn3 = 1 v, 60 mhz fundamental figure 59. in=band oip3 vs. gain over temperature; digital gain = 0000001
adrf6518 preliminary technical data rev. pra | page 18 of 36 figure 60. hd2 and hd3 vs. vpk (dc-coupled); 60 mhz tones figure 61. hd2 and hd3 vs. vpk (ac-coupled); 60 mhz tones figure 62. bandwidth vs. gain figure 63. detector output vs. pin over temperature; vgn1 = 0.5 v, vgn2/vgn3 = 0 v
preliminary technical data adrf6518 rev. pra | page 19 of 36 mixed power and filter modes vps = 3.3 v, t a = 25c, z load = 400 , digital gain code b8:b2 = 1111110, and b1 = 0 unless otherwise noted. figure 64. input impedance vs. frequency, vgn1/vgn2/vgn3 = 0 v figure 65. output impedance vs. frequency; vgn1/vgn2/vgn3 = 0 v figure 66. common-mode reje ction ratio vs. frequency figure 67. channel isolation (output to output) vs. frequency
adrf6518 preliminary technical data rev. pra | page 20 of 36 register map and cod es the filter frequency, amplifier gains, filter bypass mode , and offset correction loops can be programmed using the spi interface. table 5 provides the bit map for the internal 15 - bit register of the adrf6518 . table 4 . filter mode and power mode options filter b9 bypass active 0 vga, low power; filter off vga, low power; filter low power 1 vga, high power; filter off vga, low power; filter high power table 5 . register map msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 filter frequency code and filter bypass mode power mode vga1 gain vga2 gain vga3 gain postamp offset disable code = 1 db corner in mhz for example, 31 mhz = 011111 (msb first) use 000000 for filter bypass mode 0: l ow p ower 1: h igh p ower use 1 for filter bw > 31 mhz, in filter active mode use 1 for ch annel bw > 60 mhz, in filter bypass mode 00: 15 db 01: 12 db 10: 9 db 11: 9 db 00: 21 db 01: 18 db 10: 15 db 11: 12 db 00: 21 db 01: 18 db 10: 15 db 11: 12 db 0: 3 db 1: 9 db 0: e nable 1: d isable
preliminary technical data adrf6518 rev. pra | page 21 of 36 theory of operation the adrf6518 consists of a matched pair of input vgas followed by programmable filters, and then by a cascade of two variable gain amplifiers and output adc drivers. the filters can be bypassed and powered down through the spi interface for operation beyond the maximum filter bandwidth. the block diagram of a single channel is shown in figure 68 . the programmability of the filter bandwidth and of the pre filter - ing and post filtering fixed gains through the spi interface offers great flexibility when coping with signals of varying levels in the presence of noise and large, undesired signals near the desired band. the entire differential signal chain is dc - coupled with flexibl e interfaces at the input and output. the bandwidth and gain setting controls for the two channels are shared, ensuring close matching of their magnitude and phase responses. the adrf6518 can be fully disabled through the enbl pin. figure 68 . signal path block diagram for a single channel of the adrf6518 filtering and amplification are fundamental operati ons in any signal processing system. filtering is necessary to select the intended signal while rejecting out - of - band noise and interferers. amplification increases the level of the desired signal to overcome noise added by the system. when used together, filtering and amplification can extract a low level signal of interest in the presence of noise and out - of - band interferers. such analog signal processing alleviates the requirements on the analog, mixed signal, and digital components that follow. input v gas the input vgas provide a convenient interface to the sensitive filter sections that follow. they are designed to have a low noise figure and high linearity. the combination of analog gain control and digital gain settings allow a wide range of input si gnal levels to be conditioned to drive the filters at up to 2 v p- p amplitude. the vgas set a differential input impedance of 400 ?. the baseband input signal can be ac - coupled or dc - coupled via pin 7 selection. when the signal is dc - coupled, wide input co mmon - mode voltage is supported by having an optional 5 v supply on pin 8, vpi. the d efault common - mode voltage is vpi/2, which is available on the dual function pin 7, vicm/ac, to set the output common - mode voltage of the driving circuit . however, this is optional and input common - mode can be independently set within the supported range. for a 3.3 v supply on vpi, the input common mode can range from 1.35 v to 1.95 v, while maintaining a 5 v p- p input level at >60 dbc hd2 and hd3 . for a 5 v supply on vpi, the input common - mode range extends to 1.35 v to 3.1 v. extra current is drawn from the vpi supply to support an input common mode greater than the mid value of the main 3.3 v supply, that is, vps/2. the vicm/ac voltage is not buffered and must be sensed at a high impedance point to p revent it from being loaded down. when the baseband input signal is ac - coupled, pull the vicm/ac pin low to activate the internal bias for the input stage. the input vgas have analog gain control of 24 db , foll owed by a digital gain settings of 9 db , 12 db, or 15 db , selectable through the spi (see the register map and codes section). the vgas are based on the analog devices, inc., patented x - amp? architecture, consisting of tapped 24 db attenuators , followed by programmable gain amplifiers. the x - amp architecture gener - ates a continuous linear - in - db monotonic gain response with low ripple. the analog gain of the vga sections are controlled through the high impedance vgn1 pin with an accurate slope of 30 mv/db. adjust t he vga analog gain through an agc mechanism, such that 2 v p- p at the output of the first vga is not exceeded. if , however , the input signal is small eno ugh, the first vga can be set at full gain for best noise figure ( nf ) perfor - mance and gain control achieved in the second or third vga. driving adrf6518 single - ended the input structure of th e adrf6518 is designed for differen - tial drive. however , with some performance degradation, it can be driven single ended, especially at low bandwidth signals. see the ap plications information section for guidance on single - ended drive. peak detector to measure the signal level at the critical interface of the vga1 output and the programmable filter input, a peak detector has been implemented. the peak detector simultaneously measures both channels at the vga1 output and reports the bigger of the two at the vpk pin. the on - chip holding cap acitor and negligi - ble leak age at the internal node ensure a large droop time of the order of a millis ec ond , which is a function of the peak voltage as well. bigger peak voltage results in longer droop time. the droop time can be adjusted down by placing a resistor between the ravg and vpos pi ns . typical values of ravg can range from 1 m ? to 1 k? . a s the ravg resistor value is reduced, the peak voltage , vpk, appears as an envelope output. the peak detector has the attack bandwidth of 100 mhz. the peak detector can be used in an agc loop to set the appropri - ate signal level at the filter input. for su ch an implementation, filter vpk appropriately, considering that it is a peak hold output. a high pulse of 25 ns or longer duration applied to the sdo/rst dual function pin reset s the vpk voltage to 0 v by discharging the internal holding cap acitor .
adrf6518 preliminary technical data rev. pra | page 22 of 36 progra mmable filters the integrated programmable filter is the key signal processing function in the adrf6518 . the filters follow a six - pole butter - worth prototype response that provides a compromis e between band rejection, ripple, and group delay. the 0.5 db bandwidth is programmed from 1 mhz to 63 mhz in 1 mhz steps via the serial programming interface (spi) as described in the programming uif"%3 section. the filters are designed so that the butterworth prototype filter shape and group delay responses vs. frequency are retained for any bandwidth setting. figure 69 and figure 70 illustrate the ideal six - pole butterworth gain and group delay responses, respectively. the group delay, g , is defined as g = ??/? where: is the phase in radians. = 2 f is the frequency in radians per second. note that for a frequency scaled filter prototype, the absolute magnitude of the group delay scales inversely with the band - wi dth; however, the shape is retained. for example, the peak group delay for a 28 mhz bandwidth setting is 14 less than for a 2 mhz setting. figure 69 . sixth - order butterworth magnitude response for 0.5 db bandwidths programmed fr om 2 mhz to 29 mhz in 1 mhz steps figure 70 . sixth - order butterworth group delay response for 0.5 db bandwidths programmed to 2 mhz and 28 mhz the corner frequency of the filters is defined by rc products, which can vary by 30% in a typical process. therefore, all the parts are factory calibrated for corner frequency, resulting in a residual 7.5% corner frequency variation over the ?40c to +85c temperature range. although absolute accuracy requires calibration, the matching o f rc products between the pair of channels is better than 1% by observing careful design and layout practices. calibration and excellent matching ensure that the magnitude and group delay responses of both channels track together, a critical requirement f or digital iq - based communication systems. bypassing the filters for higher bandwidth applications, filters of the adrf6518 can be bypassed via the spi. in the bypass mode, filters are disabled and power consumption is significantly reduced. the bandwidth of cascaded vgas, which is significantly larger than 63 mhz maximum of the filters, is fully realized in the bypass mode. variable gain amp lifiers (vga s) the cascaded vga 2 and vga 3 are also based on the x - amp architecture, and each has 24 db gain range with separate high impedance gain control inputs , vgn2 and vgn3. the vga structures of the second and third vgas are identical to that of the first vga . however, these have slightly higher noise figure and less drive level capability. their output is rated at 1 v p- p for >60 dbc hd2 and hd3. depending on the input signal range, the second or third vga or both can be used for agc purposes. the critical level to consider while making this choice is the signal level at the output of the vgas, which must not exceeded 1 v p- p to maintain low distortion. the fixed gain following both of the variable gain sections can also be pro grammed to 12 db , 15 db , 18 db, or 21 db to maximize the dynamic range. 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 1m 10m 100m 1g relative magnitude (hz) frequency (hz) 09422-043 500 400 300 200 100 0 ?100 100k 1m 10m 100m group delay (ns) frequency (hz) bw = 2mhz bw = 28mhz 14x 09422-044
preliminary technical data adrf6518 rev. pra | page 23 of 36 output buffers/adc d rivers the low impedance (<10 ?) output buffers of the adrf6518 are designed to drive either adc inputs or subsequent ampli fier stages. they are capable of delivering up to 4 v p - p composite two - tone signals into 1 k? differential loads with >60 dbc imd3. the output common - mode voltage defaults to vps/2, but it can be adjusted from 900 mv to 2.0 v without loss of drive ca pability by presenting the vocm pin with the desired common - mode voltage. the high input impedance of vocm allows the adc reference output to be connected directly. even though the output common - mode voltage is adjustable and the offset compensation loop c an null the accumulated dc offsets (see the dc offset compensation loop section), it may still be desirable to ac - couple the outputs by selecting the coupling capacitors according to the load impedance and desired bandwidth. dc offset compensati on loop in many signal processing applications, no information is carried in the d c level. in fact, dc voltages and other low frequency disturbances can often dominate the intended signal and consume precious dynamic range in the analog path and bits in the data converters. these dc voltages can be present with the desired input signal or can be generated inside the signal path by inherent dc offsets or other unintended signal - dependent processes such as self - mixing or rectification. because the adrf6518 is fully dc - coupled, it may be necessary to remove these offsets to realize the maximum signal - to - noise ratio (snr). the external offsets can be eliminated with ac - coupling capacitors at the input pins ; however, that requires large value capacitors because the impedances can be fairly low, and high - pass corners may need to be <10 hz in some cases. to address the issue of dc offsets, the adrf6518 provides an offset correction loop that nulls the output differential dc level , as shown in figure 71 . if the correction loop is not required, it can be disabled through the spi port. figure 71 . offset compensation loop operates around the vga and output buffer the offset control loop creates a high - pass corner, f hp , that is superimposed on the normal butterworth filter response when filters are enabled. typically, f hp is many orders of magnitude lower than the lower programmed filter bandwidth so that there is no interaction between them. setting f hp is accomplished with capacitors, c ofs , from the ofs1 and ofs2 pins to ground. because the correction loop works around the vga sections, f hp is also dependent o n the total gain of the cascaded vgas. in general, the expression for f hp is given by f hp (hz) = 6.7 post filter linear gain / c ofs (f) where post filter linear gain is expressed in linear terms, not in decibels (db), and is the gain following the filters, which excludes the vga1 gain. note that f hp increases in proportion to the gain. for this reason, c ofs should be chosen at the highest operating gain to guarantee that f hp is always below the maximum limit required by the system. programming the adrf6518 the 0.5 db corner frequencies for both filters, the digital gains of all the vgas , and the output buffers are programmed simultane - ously through the spi port. in addition to these, ena bling the dc offset compensation loop and power mode selection are also controlled through spi port. a 16 - bit register stores the 6 - bit code for corner frequencies of 1 mhz through 63 mhz and filter bypass, as well as the codes for vga gains, and the buffe r gain (see table 5 ). the spi protocol not only allows these selec tions to be written to the data pin, but also allows the stored code to be read back via the sdo/rst pin. the latch enable (le) pin must first go to a logic 0 for a read or write cycle to begin. on the next rising edge of the clock (clk), a logic 1 on the data pin initiates a write cycle, whereas a logic 0 on the data pin initiates a read cycle. in a wri te cycle, the next 15 clk rising edges latch the desired 15 - bit code, lsb first. this results in 16 - bit code , including the first logic 1 to initiate a write cycle. when le goes high, the write cycle is completed and different codes are presented various blocks that need programming. in a read cycle, the next 15 clk falling edges present the stored 15 - bit code, lsb first. when le goes high, the read cycle is completed. detailed timing diagrams are shown in figure 2 and figure 3 . no ise characteristics the output noise behavior of the adrf6518 depends on the gain and bandwidth settings. vga1 noise dominates in the filter bypass mode and at high filter corner settings. whi le at low corner settings, filter noise tends to dominate. the filter contributes a noise spectral density profile that is flat at low frequencies, peaks near the corner frequency, and then rolls off as the filter poles roll off the gain and noise. the mag nitude of the noise spectral density contributed by the filter, expressed in nv/hz, varies inversely with the square root of the bandwidth setting, resulting in filter noise in nv that is nearly constant with the bandwidth setting. however , with vga1 nf b eing lower than the filter, vga1 tends to dominate the overall nf. at higher frequencies, after the filter noise rolls off, the noise floor is set by the vgas. each of the x - amp vga sections used in the adrf6518 contributes a fixed noise spectral density to its respective output, gain from filters c ofs ofsx ofds 50db vga output adc driver baseband outputs 09422-050
adrf6518 preliminary technical data rev. pra | page 24 of 36 independent of the analog gain setting. with the digital gain change , however, vga output noise changes, because the gain setting resistors values change. as an example, vga1 nf corresponding to a 15 db gain setting is 14 db, whereas for 9 db gain, the nf is 15.6 db. when cascaded, the total noise contributed by the vgas at the output of the adrf6518 increa ses gradually with higher gain. this is apparent in the noise floor variation at high frequencies at different vga gain settings. the exact relationship depends on the programmed fixed gain of the amplifiers. at lower frequencies within the filter bandwidt h setting, the vgas translate the filter noise directly to the output by a factor equal to the gain following the filter. at low values of vga gain, the noise at the output is the flat spectral density contributed by the last vga. as the gain increases, mo re of the filter and first vga noise appears at the output. because the intrinsic filter noise density increases at lower bandwidth settings, it is more pronounced than it is at higher bandwidth settings. in either case, the noise density asymptotically approaches the limit set by the vgas at the highest frequencies. for other values of vga gain and bandwidth setting, the detailed shape of the noise spectral density changes according to the relative contributions of the filters and vgas. because the nois e spectral density outside the filter bandwidth is limited by the vga output noise, it may be necessary to use an external, fixed frequency, passive filter prior to analog - to - digital conversion to prevent noise aliasing from degrading the signal - to - noise ratio. a higher sampling rate, relative to the maxi - mum required adrf6518 corner frequency setting, reduces the order and complexity of this external filter. distortion charact eristics to maintain low distortion through the cascaded vgas and filter of the adrf6518 , consider the distortion limits of each stage. t he first vga has higher signal handling capability and bandwidth than vga2 and vga 3, because it must cope with out - of - band signals that can be larger than the in - band signals. in the filter mode, these out - of - band signals are filtered before reaching vga 2 and vga 3. it is important to understand the signals pre sented to the adrf6518 and to match these signals with the input and output characteristics of the part. it is useful to partition the adrf651 into the front end , composed of vga1 and the f ilt er , and the back end , composed of vga2 and vga 3 and the o utput b uffers. vga1 can handle a maximum analog attenuation setting of 5 v p- p without experiencing appreciable distortion at the input. in most applications, vga1 gain should be adjusted such that t he maximum signal presented at the filter inputs (or vga2 input in filter bypass mode) is <1.5 v p- p. at this level , the front end does not limit the distortion performance. the p eak detector output, vpk , can be used as an indicator of the signal level present at this critical interface. choose t he second and third vga gains such that their output level does not exceed 1 v p- p. the output buffer gain should be set to 3 db if the desired output is <1.4 v p- p and 9 db for a desired output of >1.4 v p-p. for these signal level considerations, the out - of - band signal , if larger than the desired in - band signal, should be addressed . in filter active mode , such an out - of - band signal only affect s the vga1 operation, because it is filtered out by the filter and does not affect the following stages. in this case, a high vga2 and vg a 3 gain may be needed to raise the small desired signal to a higher level at the output. in the filter bypass mode, such out - of - band signals may need to be filtered prior to the adrf6518 . the overall distortion introduced by the part depends on the input drive level, including the out - of - band signals, and the desired output signal level. to achieve best distortion performance and the desired overall gain , keep in mind the maximum signal levels indicated previously when selecting differe nt vga gains . to distinguish and quantify the distortion performance of the input section, two different ip3 specifications are presented. the first is called in - band ip3 and refers to a two - tone test where the signals are inside the filter bandwidth. this is exactly the same figure of merit familiar to communications engineers in which the third - order intermodulation level, imd3, is measured. to quantify the effect of out - of - band signals, a n ew out - of - band (oob) iip3 figure of merit is introduced. this test also involves a two - tone stimulus; however, the two tones are placed out - of - band so that the lower imd3 product lands in the middle of the filter pass band. at the output, only the imd3 pro duct is visible because the original two tones are filtered out. to calculate the oob ip3 at the input, the imd3 level is referred to the input by the overall gain. the oob iip3 allows the user to predict the impact of out - of - band blockers or interferers a t an arbitrary signal level on the in - band performance. the ratio of the desired input signal level to the input - referred imd3 at a given blocker level represents a signal - to - distortion limit imposed by the out - of - band signals. maximizing the dynam ic range when used in the filter mode, the role of the adrf6518 is to increase the level of a variable in - band signal while minimizing out - of - band signals. ideally, this is achieved without degrading the snr of the incoming signal or introducing distortion to the incoming signal. the first goal is to maximize the output signal swing, which can be defined by the adc input range or the input signal capacity of the next analog stage. for the complex waveforms often encoun - tered in communication systems, the peak - to - average ratio, or crest factor, must be considered when choosing the peak - to - peak output. from the chosen output signal and the maximum gain of the adrf6518 , the minimum input level can be defined. as the input signal level increases, the vga3 gain is reduced from its maximum gain point to maintain the desired fixed output level. vga2 and vga 1 can then be adjusted as the input
preliminary technical data adrf6518 rev. pra | page 25 of 36 signal level keeps increasing. this maintain s the best nf for the cascaded chain. the output noise, initially dominated by the filter and vga1 combination, follows the gain reduction, yielding a progressively better snr. at some point, the vga 3 and vga 2 gains dr op sufficiently so that their noise becomes dominant, resulting in a slower reduction in snr from that point. from the perspective of snr alone, the maximum input level is reached when the vga1 reaches its minimum gain. distortion must also be considered w hen maximizing the dynamic range. at low and moderate signal levels, the output distortion is constant and assumed to be adequate for the selected output level. at some point, the input signal becomes large enough that distortion at the input limits the sy stem. this can be kept in check by monitoring peak detector voltage, vpk. the most challenging scenario in terms of dynamic range is the presence of a large out - of - band blocker accompanying a weaker in - band wanted signal. in this case, the maximum input level is dictated by the blocker and its inclination to cause distortion. after filtering, the weak wanted signal must be amplified to the desired output level, possibly requiring maximum gain on vga2 and vga 3. in such a case, both the distortion limits asso ciated with the blocker at the input and the snr limits created by the weaker signal and higher gains are present simultaneously. furthermore, not only does the blocker scenario degrade the dynamic range, it also reduces the range of input signals that can be handled because a larger part of the gain range is simply used to extract the weak desired signal from the stronger blocker. key parameters for q uadrature - based receivers the majority of digital communication receivers make use of quadrature signaling, in which bits of information are encoded onto pairs of baseband signals that then modulate in - phase (i) and quadrature (q) sinusoidal carriers. both the baseband and modulated signals appear quite complex in the time domain with dramatic peaks and valleys . in a typical receiver, the goal is to recover the pair of quadrature baseband signals in the presence of noise and interfering signals after quadrature demodulation. in the process of filtering out - of - band noise and unwanted inter - ferers and restoring th e levels of the wanted i and q baseband signals, it is critical to retain their gain and phase integrity over the bandwidth. in the filter mode, the adrf6518 delivers flat in - band gain and gro up delay, consistent with a six - pole butterworth prototype filter, as described in the programmable filters section. furthermore, careful design ensures excellent matching of these parameters between the i and q channels. although absolute gain flatness and group delay can be corrected with digital equalization, mismatch introduces quadrature errors and intersy mbo l inter ference that degrade bit error rates in digital communication systems. for wideband signals, filters can be bypassed and the adrf6518 then be comes a dual cascaded chain of three vg a s, offe ring large gain range options , while maintaining gain and group delay match between the two channels.
adrf6518 preliminary technical data rev. pra | page 26 of 36 applications informa tion basic connections figure 72 shows the basic connections for a typical adrf651 8 application. supply decoupling apply a nominal supply voltage of 3.3 v to the supply pins , vps, vpi , and vp sd . the supply voltage must not exceed 3.45 v or drop below 3.15 v for vps and vpsd . the supply voltage on vpi must not exceed 5.25 v. decouple e ach supply pin to ground with at least one low inductance, surface - mount ceramic capacitor of 0.1 f placed as close as possible to the adrf651 8 device. the adrf6 518 has two separate supplies: an analog supply and a digital supply. take c are to separate the analog and digital supplies with a large surface - mount inductor of 33 h. each supply should then be decoupled separately to its respective ground through a 10 f capacitor. input signal path each signal path has input buffers, accessed through the inp1, inm1, inp2, and inm2 pins, that set a differential input impedance of 400 ?. these inputs sit at a nominal common - mode voltage around midsupply. the inputs can be dc - coupled or ac -coupled. to ac couple the inputs , the user must p ull the vicm/ac pin to ground. this provides an input common - mode voltage of vpi/2. to dc couple the inputs, let the vicm pin float. if using direct dc coupling, the common - mode voltage, v cm , can range from 1.35 v to 2.0 v while vpi = 3.3 v . the user has the option of tying vpi to a voltage up to 5 v. this provides a common - mode range of 1.35 v to 3.1 v. in general, the minimum input common - mode voltage is always 1.35 v, but the maximum common - mode voltage is v cm_max = 0.64 v vpi ? 0.135 v. the vicm pin can be used as a reference common - mode voltage for driving a high impedance sensing node of the preceding cascaded part (vicm has a 7 k? impedance). output signal path the low impedance ( 10 ?) output buffers are designed to drive a high impedance load, such as an adc input or another amplifier stage. the output pins opp1, opm1, opp2, and opm2 sit at a nominal output common - mode voltage of vps/2, but ca n be driven to a voltage of 0. 9 v to 2. 1 v by applying the desired common - mode voltage to the high impedance vocm pin. dc offset compensati on loop enabled when the dc offset compensation loop is enabled via b1 of the spi register, the adrf6518 can null the output differential dc level. the loop is enabled by setting b1 = 0. the offset compensation loop creates a high - pass corner frequency, which is proportional to the value of the capacitors that are connected from the ofs1 and ofs2 pins to ground. for more information about setting the high - pass corner frequency, see the dc offset compensation loop section. figure 72 . basic connections
preliminary technical data adrf6518 rev. pra | page 27 of 36 common- mode bypassing the adrf6518 common - mode pins, vicm /ac and vocm, must be decoupled to ground. at least one low inductance, surface - mount ceramic capacitor with a value of 0.1 f must be used to decouple the common - mode pins. serial port connecti ons the adrf6518 has a spi port to control the gain and filter band - width settings. data can be written to the internal 15 - bit register and read from the register. it is recommended that low - pass rc filtering be placed on the spi lines to filter out any high frequency glit ches. see figure 74 , the evaluation board schematic, for an example of a low - pass rc filter. enable/disable funct ion to enable the adrf6518 , the enbl pin must be pulled high. driving the enbl pin low disables the device, reducing current consumption to approximately 9 ma at room temperature. g ain pin decoupling t he adrf6518 has three analog gain control pins: vgn1, vgn2, and vgn3. use a t least one low inductance, surface - mount ceramic capacitor with a value of 0.1 f to decouple each gain control pin to ground. peak d etector c onnections t he adrf6518 has p eak detector output on the vpk pin, with a s caling of 1 v/v pk differential at filter inputs. the b igger peak of the two channels reported. the p eak detector time - constant can be changed with a resistor from the ravg pin to vps. leave the ravg pin open for the longest time - constant ( hold time ) . ravg resistor range is to 1 k . to reset the peak detector, pull the sdo/rst pin high for 25 ns or longer. logic levels are v low < 0.8 v, v high > 2 v. error vector magnitu de (evm) performance error vector magnitude (evm) is a measure used to quantify the performance of a digital radio transmitter or receiver by measuring the fidelity of the digital signal transmitted or received. various imperfections in the link, such as magnitude and phase imbalance, noise, and distortion, cause the constellation points to deviate from their ideal locations. in general, a receiver exhibits three distinct evm limitations vs. received input signal power. as signal power increases, the distortion com ponents increase. ? at large enough signal levels, where the distortion compo - nents due to the harmonic nonlinearities in the device are falling in - band, evm degrades as signal levels increase. ? at medium signal levels, where the signal chain behaves in a linear manner and the signal is well above any notable noise contributions, evm has a tendency to reach an opti - mal level determined dominantly by either the quadrature accuracy and iq gain match of the signal chain or the precision of the test equipment. ? as signal levels decrease, such that noise is a major con - tributor, evm performance vs. the signal level exhibits a decibel - for - decibel degradation with decreasing signal level. at these lower signal levels, where noise is the dominant limitation, decibel evm is directly proportional to the snr. evm test setup the basic setup to test evm for the adrf6518 consisted of an agilent mxg m5182b vector signal generator used as a signal source and a agilent dso7104b oscilloscope used to sample the signal while connected to a computer running agilent 89600 vsa software to calculate the evm of the signal. the m5182b iq baseband differenti al outputs drove the adrf6518 inputs. the i and q outputs of the adrf6518 were loaded with 400 ? differential impedances and connected differentially to two ad8130 differential amplifiers to convert the signals into single - ended signals. the sin gle- ended signals were connected to the input channels of the vsa.
adrf6518 preliminary technical data rev. pra | page 28 of 36 evaluation board an evaluation board is available for testing the adrf6518 . evaluation board con trol software the adrf6518 evaluation board is controlled through the parallel port on a pc. the parallel port is programmed via the adrf6518 evaluation software. this software enables/disables the dc offset compensation loop and controls the filter corner frequency, the high and l ow power mode s, and the minimum and maximum gains for each amplifier in the adrf6518 . for information about the register map, see table 5 . for information about spi port timing and control, see figure 2 and figure 3 . after the software is downloaded and insta lled, start the basic user interface to program the filter corner and gain values (see figure 73 ). to program the filter corner, pe r form one of the following: ? click the arrow in the frequency corner mhz section of the window, select the desired corner frequency from the menu, and click write selected cutoff frequency to device . ? click frequency +1 mhz or frequency ?1 mhz to increment or decrement the frequency co rner in 1 mhz steps from the current frequency corner. to program the filter mode, offset correction, and power mode, move the respective slider switch in the upper right corner of the window . to program the maximum gain s of vga1, vga2, vga3 , and the post amplifier , click the vga1 gain db , vga2 gain db , vga3 gain db , and post amp gain db drop - down box es and select the desired gain. ? the vga1 maximum gain can be set to 9 db, 12 db , or 15 db. ? the vga2 and vga3 maximum gain can be set to 12 db, 15 db, 18 db , o r 21 db. ? the postamplifier maximum gain can be set to 3 db or 9 db. when the user clicks the write selected cutoff frequency to device button, a write operation is executed, immediately followed by a read operation. the updated information is displayed in the vga1 gain db , filter corner mhz , vga2 gain db , vga3 gain db , and post amp gain db fields. figure 73 . analog devices adrf6518 evaluation software
preliminary technical data adrf6518 rev. pra | page 29 of 36 schematics and artwo rk figure 74 . evaluation board schematic
adrf6518 preliminary technical data rev. pra | page 30 of 36 figure 75 . usb evaluation board schematic 56 55 54 53 52 51 50 49 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 35 36 37 38 39 40 41 42 pd7_fd15 pd4_fd12 pd6_fd14 pd5_fd13 gnd clkout gnd vcc pa5_fifoard1 pa2_sloe reset_n pa3_wu2 pa4_fifoard0 pa6_pktend pa7_flagd_scls_n gnd vcc sda pb4_fd4 pb3_fd3 pb0_fd0 scl pb1_fd1 pb2_fd2 dplus xtalout xtalin rdy1_slwr avcc avcc agnd rdy0_slrd cy7c68013a-56 l txc u4 le 9 dminus 10 agnd 11 vcc 12 gnd 13 ifclk 14 reserved 23 pb5_fd5 24 pb6_fd6 27 vcc 25 pb7_fd7 26 gnd 28 gnd 29 30 31 32 33 34 ctl1_flagb pa1_int1_n ctl0_flaga ctl2_flagc vcc pa0_int0_n 48 47 46 45 44 43 wakeup vcc pd0_fd8 pd1_fd9 pd3_fd11 pd2_fd10 clk dat a 3v3_usb 3v3_usb 3v3_usb c48 10pf c49 0.1f 3v3_usb 3v3_usb r61 2k? cr2 3v3_usb r64 0? c37 0.1f c45 0.1f r62 100k? 3v3_usb y1 24mhz 3 4 2 1 c54 22pf c51 22pf 1 2 3 4 5 g1 g2 g3 g4 5v_usb p5 1 2 3 4 5 6 7 8 a0 a1 a2 gnd sda scl wc_n vcc 3v3_usb 3v3_usb 24lc64-i_sn u2 adp3334 u3 1 8 2 3 4 7 6 5 out1 out2 fb nc in2 in1 sd gnd c47 1.0f r65 2k? cr1 5v_usb r69 78.7k? c50 1000pf r70 140k? c52 1.0f 3v3_usb dgnd c35 0.1f c42 0.1f c36 0.1f c41 0.1f c40 0.1f c44 0.1f c46 0.1f 3v3_usb r60 2k? r59 2k? c38 10pf c39 0.1f sdo 09422-159
preliminary technical data adrf6518 rev. pra | page 31 of 36 figure 76 . top layer silkscreen figure 77 . component side layout table 6 . evaluation board configuration options co mponents function default conditions c1, c2, c4, c11, c12, c15, c16, c30, c31, l1, l2, r2, r 3, p4 power supply and ground decoupling. nominal supply decoupling consists of a 0.1 f capacitor to ground. c1, c2 , c30 = 10 f (size 1210) c4, c11, c12, c15, c16 , c31 = 0.1 f (size 0402) l1, l2 = 33 h (size 1812) r2, r3 = 0 (size 0402) p4 = i nstalled t1, t2, c3, c6, c7 to c10, r31, r32, r43, r44, r45, r46, r47, r48, r49, r50 input interface. the inp1 _se , inm1, inp2_se, and inm2 input smas are used to drive the part differentially by bypassing the baluns. using only in p 1_se and inp2_se in conjunction with the baluns enables single - ended operation. the default configuration of the evaluation board is for single - ended operation. t1 and t2 are 8:1 impedanc e ratio baluns that transform a single - ended signal in a 50 system into a balanced differential signal in a 400 system. r31, r32, r47, r48, r49, and r50 are populated for appropriate balun interface t1, t2 = pulse electronics cx2049lnl c3, c6 = 0.1 f (size 0402) c7 to c10 = 0.1 f (size 0602) r31, r32, r47 to r50 = 0 (size 0402) r43 to r46 = open (size 0402)
adrf6518 preliminary technical data rev. pra | page 32 of 36 co mponents function default conditions to bypass the t1 and t2 baluns for differential inter facing, remove the balun interfacing resistors , r31, r32, r47, r48, r49, and r50, and populate r43, r44, r45, and r46 with 0 resistors. t3 , t 4 , c 19 to c 24, r5, r6 r 19, r 20, r35 to r42 output interface. the opp1, opm1 _se , opp2, and opm2_se output smas are used to obtain differential signals from the part when the output baluns are bypassed. using op m 1_se, opm2_se, and the baluns, the user can obtain single - ended output signals. the default configuration of the evaluation board is for single - ended operation. t3 and t4 are 8:1 impedance ratio baluns that transform a differential signal in a 400 system into a single - ended signal in a 50 system. to bypass the t3 and t4 baluns for differential interfacing, remove the balun interfacing resistors , r19, r20, r35, r36, r41, and r42, and populate r37, r38, r39, and r40 with 0 resistors. r5 and r6 can be populated with an impedance of at least 400 to terminate the output in differential applications. t3, t4 = pulse electronics cx2049lnl c19 to c2 4 = 0.1 f (size 0402) r5, r6 = open (size 0402) r19, r20, r35, r36, r41, r42 = 0 (size 0402) r 37 to r 40 = open (size 0402) p2 enable interface. the adrf6518 is powered up by applying a logic high voltage to the enbl pin (jumper p2 is co nnected to vps). p2 = installed for enable p3, r1, r17, r18, r21, r63 , c25, c53, c55, c56 serial control interface. the digital interface sets the corner frequency, vga1/vga2/vga 3 maximum gain s , and the postamplifier maximum gain using the serial interface via the le, clk, data, and sdo pins. rc filter networks can be populated on the clk , le , and data lines to filter the spi signals. clk, data, and le signals can be observed via p3 for debug purposes. setting c25, c53, and c56 = 330 pf is recommending for filtering. p 3 = installed r1 = 0 (size 0402) r2 1 = 10 k (size 0402) c2 5 , c 53, c55, c56 = open (size 0402) r17, r 18, r 6 3 = 1 k (size 0402) c13, c14 dc offset compensation loop. the dc offset compensation loop is enabled via the spi port. when enabled, the c13 and c14 capacitors are connected to circuit common. the high - pass corner frequency is expressed as follows: f hp (hz) = 6.7 ( post filter linear gain / c ofs (f)) c13, c14 = 0.1 f (size 0402) c5 input common - mode reference . the input common - mode voltage can be monitor ed at the vicm pin. if the vicm pin is left open, an input common - mode voltage must be supplied externally ( dc coupling mode). if vicm pin is connected to ground, the input common - mode defaults to vpi /2 (ac coupling mode) . c5 = 0.1 f (size 0402) c18 output common - mode setpoint. the output common - mode voltage can be set externally when applied to the vocm pin. if the vocm pin is left open, the output common - mode voltage defaults to vps/2. c18 = 0.1 f (size 0402) c17, c2 7, c32 analog gain control. the range of the analog gain pin s, vgn1, vgn2, and vgn3 , is from 0 v to 1 v, creating a gain scaling of 30 mv/db. c17 , c27, c32 = 0.1 f (size 0402) p1, r4, r15, c33, c34 peak detector. p1 = i nstalled r4 = 0 (size 0402) r15, c33, c34 = open (size 0402) u1 , u2 , u3 , p5 cypress microcontroller, eeprom, and ldo u2 = microchip micro24lc64 u3 = analog devices adp3334acpz u4 = cypress semiconductor cy7c68013a - 56 lt xc p5 = mini usb connector c35, c36, c40, c41, c42, c44, c46 3.3 v supply decoupling. several capacitors are used for decoupling on the 3.3 v supply. c35, c36, c40, c41, c42, c44, c46 = 0.1 f (0402) c37, c38, c39, c45 , c48, c49, r59, r60, r61, r62, r64, cr2 cypress and eeprom components. c38, c4 8 = 10 pf (0402) c37, c39, c45, c49 = 0.1 f (0402) r59, r60, r61 = 2 k (0402) r62, r64 = 100 k (0402) cr2 = rohm sml - 21omtt86
preliminary technical data adrf6518 rev. pra | page 33 of 36 co mponents function default conditions c47, c50, c52, r65, r69, r70, cr1 ldo components . c47, c52 = 1 f (0402) c50 = 1000 pf (0402) r65 = 2 k (0402) r69 = 78.7 k (0402) r70 = 140 k (0402) cr1 = rohm sml - 21omtt86 y1, c51, c54 crystal oscillator and components. 24 mhz crystal oscillator. y1 = ndk nx3225sa - 24mhz c51, c54 = 22 pf (0402)
adrf6518 preliminary technical data rev. pra | page 34 of 36 outline dimensions figure 78 . 32 - lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp - 32 - 13) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adrf6518acpz - r7 ?40c to +85c 32 - lead lfcsp_wq, 7 tape and reel cp - 32 - 13 adrf6518acpz -wp ?40c to +85c 32 - lead lfcsp_wq, waffle pack cp -32 -13 adrf6518 - evalz evaluation board 1 z = rohs compliant part. 05-24-2012- a 1 0.50 bsc bot t om view top view pin 1 indic at or 32 9 16 17 24 25 8 exposed pa d pin 1 indic at or sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min 3.45 3.30 sq 3.15 compliant to jedec standards mo-220- whhd . 3.50 ref
preliminary technical data adrf6518 rev. pra | page 35 of 36 notes
adrf6518 preliminary technical data rev. pra | page 36 of 36 notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr11449 -0- 5/13(pra)

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